In the manufacture of integrated circuits and other electronic components, the stacking or vertical positioning of circuit trace wires and electronics such as CPU packages, memory, resistors, and the like is advantageous in both minimizing motherboard space, and reduces conductor track length and routing of interconnections between interoperating parts, thereby achieving faster signal propagation and reduced noise.
Conventionally, when forming stacked or multi-layer circuit constructs such as package on package (PoP) integrated circuits and the like (hereinafter also generally referred to as packages), individual circuit layers are formed by photo-masking and trace printing individual silicon substrates. The substrates of uniform thickness are then vertically aligned and attached, as for example by the selective formation and subsequent infilling of through hole vias and the like.
High density three-dimensional interconnection and packaging technology shows promise in providing interconnection among devices of diverse technological origin, including microelectronic, micro and electro-mechanical, MEMS, NEMS, photonic and microfluidic devices. As well, devices operating functionality by analog, digital, memory, power, acoustical, electromagnetic, optical and/or microfluidic operation have been identified as a critical area of development to meet the emerging requirements of the electronic industry. The 3-D package technology shows promise in realizing high performance memory and MEMS-integrated circuit integration. Conventional packaging technologies may however, be inadequate to meet industry demands of diverse high density low power integration.
To at least partially overcome limitations of the existing multi-chip technologies like MCM-C, MCM-D, and to meet growing high density interconnect demands of the industry, through-silicon-via (TSV) technology (lowest 5 μm diameter, 10 μm pitch) has been developed to enable connection of three-dimensional stacked devices, such as 3-D-IC (stacking of transistors), 3-D-SIC (3-D stacked integrated circuit), and 3-D SOC (3-D System-on-Chip). In conventional via formation, dies are thinned to 20-30 μm, and copper filled interconnects or through-silicon vias (TSV) passing through the wafers are used to achieve connection from one level to another level. Heretofore, wider via pads have proven necessary that limit the interconnection density. As well, thermomechanical reliability problems caused by TSV-induced stress, electronic performance degradation due to strained silicon, and possible device failure due to imperfect TSVs are among the biggest challenges in 3-D integrated circuits.
Fraunhofer IZM recently developed a power embedding packaging technology that seeks to eliminate conventional wire bonding to connect individual integrated circuits with other integrated circuits to realize a system capable of handling high power. However this technology is limited to organic substrates, and necessitates laser drilling of vias in the organic substrates once it encapsulates the die. In addition, as a result of manufacturing limitations, conventional 3D package technologies described above allow only for vertical integration in a single direction only.